Senior Analog IC Layout Engineer

NXP Semiconductors is seeking an experienced Senior Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS). This role involves driving layout execution from planning through tape-out for complex automotive mixed-signal and power management ICs, collaborating with global engineering teams.

NXP Semiconductors N.V. is a trusted partner for innovative solutions in the automotive, industrial & IoT, mobile, and communications infrastructure markets. With operations in over 30 countries and a commitment to sustainability and an inclusive work environment, NXP fosters a culture of "Brighter Together" to build game-changing solutions.

We are looking for a candidate to lead physical implementation, define floorplans, and ensure design quality. If you have strong experience in Analog IC Layout development and expertise with Cadence Virtuoso, we encourage you to apply.

Company Overview

NXP Semiconductors N.V. (NASDAQ: NXPI) is a global leader in secure connectivity solutions for automotive, industrial & IoT, mobile, and communication infrastructure markets. The company is committed to developing innovative solutions that make the world better, safer, and more secure, with a strong focus on sustainability and diversity.

Quick Details

• Salary Range: Not Specified
• Job Type: Full-time
• Qualifications: Bachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics
• Experience: Strong experience in Analog IC Layout development

Key Responsibilities

• Lead the physical implementation of Analog and Mixed-Signal integrated circuits.
• Define and optimize floorplans for complex blocks and top-level assemblies.
• Drive layout activities from planning through tape-out.
• Own DRC, LVS, ERC and physical sign-off activities.
• Coordinate layout activities with Design, Verification, Package, Test and Product Engineering teams.

Requirements

• Strong experience in Analog IC Layout development.
• Expertise with Cadence Virtuoso Layout environment.
• Experience with DRC/LVS sign-off methodologies.
• Solid understanding of CMOS, BCD, SOI and Mixed-Signal design environments.
• Ability to work independently and manage complex technical challenges.
• Fluent written and spoken English.

Benefits

• Career Development Opportunities with online and offline learning.
• Commitment to sustainability and an inclusive work environment.
• Opportunities to work on advanced automotive and industrial semiconductor products.
• Contribute to layout methodology improvements and best practices.
• Potential for technical leadership and mentoring junior engineers.